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Job Title: Emulation Engineer
Location: Bangalore
Experience Required: 8 to 12 Years

Key Responsibilities:

1. RTL Design and Testbench Development:

   • Proficient in Verilog, VHDL, and System Verilog for creating and debugging RTL designs.
   • Develop and write testbenches to validate and verify design functionality.

2. Emulation and Simulation Flow:

   • Manage front-end and back-end compilation processes for emulation and simulation of complex digital systems.
   • Ensure smooth execution of emulation flows from RTL design to hardware validation.

3. Debugging:

   • Perform comprehensive RTL debugging using advanced techniques such as triggers and System Verilog Assertions (SVA).
   • Utilize the Verdi tool for efficient debugging and problem resolution.

4. Scripting and Automation:

   • Develop and maintain automation scripts using Python and TCL to streamline verification and testing processes.

5. Pre-Silicon Validation:

   • Execute pre-silicon validation processes, ensuring the integrity and performance of designs before fabrication.

6. Cross-functional Collaboration:

   • Work closely with design, verification, and hardware teams to achieve successful emulation and validation outcomes.

7. Problem-solving and Innovation:

   • Provide solutions to design challenges, identify bottlenecks in the verification process, and propose enhancements for efficiency.